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On the other hand, when the voltage input to QT1 falls below the two diode threshold level, QT1 and QT2 are turned off thereby raising the voltage level at the output OUT to Vcc representing a logical one.
The converter circuit 10 includes a high impedance current mirror circuit section including transistors QD and Q2. Schottky transistor Q1 is provided in the preferred embodiment to raise the quiescent voltage level of the converter circuit where it is coupled to TTL gate 14 to approximately the threshold level of TTL gate If the TTL gate 14 has only a one diode voltage threshold level, then Q1 is unnecessary.
Transistor QD has its base and collector shorted together and consequently functions as a diode. The base of transistor QD is coupled to the base of transistor Q2. The emitters of transistors QD and Q2 are coupled to a reference potential such as ground shown in the drawings. The collector of Q2 is coupled to the base of transistor Q1. The collector of transistor QD is coupled to the emitter of transistor Q1.
This current mirror section provides two parallel current paths in which the amount of current in each path is maintained uniform. With reference to FIG. Hence, the current in one path is a mirror image of the current in the other path. This is due to the fact that the bases of QD and Q2 are biased at the same potential since they are coupled together.
Since QD and Q2 are matched devices, their emitter currents will be the same. Consequently, their collector currents ID and IC2, respectively, will remain equal since the current gain factor Beta of the transistors is much greater than one and there is negligible base current. The collector of Q2 and base of Q1 are coupled through a resistor R2 to the emitter of transistor Q4.
Similarly, the collector of Q1 is coupled to the emitter of Q3 through a second resistor R1. Both resistors are of equal value and Q3 and Q4 are matched devices. The collectors of transistors Q3 and Q4 are coupled to a power supply voltage Vcc of about 5. Similarly, the base of transistor Q4 is coupled to the collector of transistor QC2.
Thus, the converter circuit 10 is coupled to CML gate 12 in an emitter follower configuration. The advantage of the emitter follower configuration is that it presents little loading to the CML gate 12 since it has a high input impedance and low output inpedance. Consequently, overall delay time is minimized. The nomenclature of FIG. The current gain factor, beta B , is much greater than one for the transistors in converter 10 and consequently the base current to the transistors is negligible.
Since QD and Q2 are matched devices, the current through each device will be the same, i. ID equals IC2. Since the current IB1 to transistor Q1 is negligible, the collector to emitter current IC1 of transistor of Q1 also equals the collector to emitter current IC2 of transistor Q2.
In such case, the emitter currents I1 and I2 emanating from transistors Q3 and Q4 will be the same. This can be represented by the equation. The emitter current I1 will also be equal to the emitter current I2 due to the current reflection characteristics of the current mirror circuit section which it is coupled. In such case, the Schottky diode portion of transistor Q1 will be forward biased and part of the current I2 will be shunted through the Schottky diode in order to maintain the current reflection requirement of IC1 equal to IC2.
Furthermore, the low forward voltage and high speed characteristics of a Schottky diode helps to prevent transistor Q1 from going into deep saturation. When the differential voltage is greater than the forward voltage of Schottky diode portion of Q1, the current IC1 is equal to the summation of the current I1 plus IS.
The current IC2 in the other leg of the current reflection section is equal to the current I2 minus IS where IS is approximately equal to IB1 due to the high current gain factor, beta, of the transistor. The purpose of this current will become more apparent later in the description of the preferred embodiment. Assume now that the voltage V1 at the base of transistor Q3 is now greater than the voltage V2 at the base of transistor Q4, for example, due to a logical zero input at IN of CML gate Accordingly, from equation 5.
When the converter circuit 10 is coupled to the TTL gate 14 as shown in the drawing, current is steered into or out of TTL gate 14 to quickly turn it on or off depending upon the differential voltage sensed in CML gate I have decided to use CHg IC. And this IC is now easily available in India. Above is the implemented schematic.
The schematic I got from CHg in Eagle. Not much explanation is required as its a very simple circuit. Still if you have any queries you are free to ask. Truly speaking this converter board is the only reason that it was possible to make this project. I have used points GL12 Breadboard over here. It was too big instead you can also use point Mini breadboard. No project is complete without jumper wires. Over here I have used male to male jumper wires.
I have also used the same wires for connecting the USB B connector to breadboard.
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